Analog Devices Inc. AD9554 Clock Translator
Analog Devices Inc. AD9554 Clock Translator is offers a low loop bandwidth and is designed to provide jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The AD9554 dissipates only 940mW of power while generating up to eight output clocks over an output range of 430kHz to 941MHz, synchronized to four 2kHz to 1GHz external input references, with a loop bandwidth as low as 0.1Hz.
The AD9554 clock's high level of integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250fs over the 50kHz to 80MHz range and 350fs over the 12kHz to 20MHz range. The four analog-digital phase-locked loops (ADPLL) allow for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. AD9554 operates over an industrial temperature range of −40°C to +85°C and is ideal for network synchronization, cleanup of reference clock jitter, SONET/SDH clocks up to OC-192, including FEC, Stratum 3 holdover, jitter cleanup, and phase transient control, cable infrastructure, and data communications.
Features
- Supports GR-1244 Stratum 3 stability in holdover mode
- Supports smooth reference switchover with virtually no disturbance on output phase
- Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
- Supports ITU-T G.8262 synchronous Ethernet slave clocks
- Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261
- Auto/manual holdover and reference switchover
- Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
- Quad analog digital phase-locked loop (DPLL) architecture with
- Four reference inputs (single-ended or differential)
- Eight outputs (single-ended or differential)
- 4 × 4 crosspoint allows any reference input to drive any PLL
- Input reference frequencies from 2kHz to 1000MHz
- Reference validation and frequency monitoring: 2ppm
- Programmable input reference switchover priority
- 20-bit programmable input reference divider
- 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECL-compatible
- 430kHz to 941MHz Output frequency range
- Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL
- Programmable loop bandwidths from 0.1Hz to 4kHz
- Loop bandwidth as low as 0.1Hz to guarantee SyncE compliance
- Optional off-chip EEPROM to store power-up profile
- 72-lead (10mm × 10mm) LFCSP package
Applications
- Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping
- Cleanup of reference clock jitter
- SONET/SDH clocks up to OC-192, including FEC
- Stratum 3 holdover, jitter cleanup, and phase transient control
- Cable infrastructure
- Data communications
Block Diagram
Evaluation Board
Analog Devices Inc. AD9554/PCBZ Evaluation Board
Eval board for AD9554 multi-service adaptive quad-channel clock translator w/clock multiplier.