Alliance Memory DDR1 Synchronous DRAM

Alliance Memory DDR1 Synchronous DRAM is a high-speed CMOS double data rate synchronous DRAM. It is internally configured with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK. Read and write accesses to the SDRAM are burst oriented. The Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The DDR SDRAM provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, The DDR SDRAM features a programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance.


  • Fast clock rate of 200MHz
  • Differential Clock CK & CK
  • Bi-directional DQS
  • DLL enable/disable by EMRS
  • Fully synchronous operation
  • Internal pipeline architecture
  • Four internal banks
  • Programmable Mode and Extended Mode registers
  • Burst Type: Sequential & Interleaved
  • Individual byte write mask control
  • DM write latency = 0
  • Auto-refresh and self-refresh
  • Commercial operating temperature range: 0°C~ 70°C
  • Industrial operating temperature range: -40°C~ 85°C
  • Precharge & active power down
  • Interface: SSTL_2 I/O Interface
  • Package: 66-pin TSOP II, 0.65mm pin pitch
  • Lead and Halogen-free
Publicado: 2014-02-27 | Actualizado: 2022-03-11